After the launch of the 2nd Generation of processors AMD EPYC 'ROME', where there are a total of 9 models, now we know that the company prepares nothing less than 15 different CPUs for the 3rd Gen baptized as AMD EPYC Milan.
If the data is correct, the top-of-the-range model will include nothing less than 10 dies to add a maximum of 80 cores attached to an Octa memory controller(8)-Channel, there are many variants with fewer cores, but where this free space could be used by adding HBM memory to substantially improve speeds alongside the already known I / O Die. In this way the company could include a maximum of 10 die (80 cores) with space for 4 HBM memory chips; and I / O DIe or for example choose 8 die (64 cores) + 6 die of HBM memory + I / O Die, so the company will have great control over the customization of silicon.
A design based on an interposer (intermediary) with integrated HBM memory could offer much faster access and transfer times than traditional DDR-based memory, where the DDR channel can act as a bottleneck. With interconnection, I / O and interposer, eliminating existing bottlenecks when joining the CPU with HBM memory will lead to significant accelerations for applications that rely heavily on memory, taking into account that this configuration will result in speed much faster compared to the standard memory we have today, that is, DDR4 RAM.
It is worth mentioning that the previous leaks have indicated that AMD Milan has an 8 + 1 design, that is: 64 cores + 1 HBM memory chip, a fairly logical move by AMD due to the limitations of DDR4 memory, something that DDR5 could solve in the future, so with DDR5 memory we could see even a CPU with 14 die (112 cores) + the I / O Die.